From nobody Wed Apr 3 13:35 EST 1996 Date: Wed, 3 Apr 1996 13:35:38 -0500 (EST) From: uid no body To: techreps@cs.buffalo.edu Subject: techrep: POST request Content-Type: text Content-Length: 1076 ContactPerson: vpd@cs.buffalo.edu Remote host: hadar.cs.buffalo.edu Remote ident: vpd ### Begin Citation ### Do not delete this line ### %R 96-08 %U /cad/vpd/power/Burn_In/Dynamic/doc/ICCAD96/iccad.ps %A Dabholkar, Vinay P. %A Chakravarty, Sreejit %T Dynamic Stress Tests for ``Narrow Metal Imperfections'' in Full Scan Circuits %D April 03, 1996 %I Department of Computer Science, SUNY Buffalo %K Stress tests, Dynamic burn-in %X Dynamic stress testing is an important process that is used to improve the reliability of circuits. In this paper, we investigate the problem of computing cyclic sequences which can be used during burn-in of full scan circuits. Using a switching activity model we show that the stress due to electromigration and hot-electron degradation can be accurately modeled. Notwithstanding the difficulty of computing optimal dynamic stress tests, we demonstrate experimentally that efficient heuristics can be developed to compute good dynamic stress tests for full scan circuits.